41 research outputs found
Image recognition with an adiabatic quantum computer I. Mapping to quadratic unconstrained binary optimization
Many artificial intelligence (AI) problems naturally map to NP-hard
optimization problems. This has the interesting consequence that enabling
human-level capability in machines often requires systems that can handle
formally intractable problems. This issue can sometimes (but possibly not
always) be resolved by building special-purpose heuristic algorithms, tailored
to the problem in question. Because of the continued difficulties in automating
certain tasks that are natural for humans, there remains a strong motivation
for AI researchers to investigate and apply new algorithms and techniques to
hard AI problems. Recently a novel class of relevant algorithms that require
quantum mechanical hardware have been proposed. These algorithms, referred to
as quantum adiabatic algorithms, represent a new approach to designing both
complete and heuristic solvers for NP-hard optimization problems. In this work
we describe how to formulate image recognition, which is a canonical NP-hard AI
problem, as a Quadratic Unconstrained Binary Optimization (QUBO) problem. The
QUBO format corresponds to the input format required for D-Wave superconducting
adiabatic quantum computing (AQC) processors.Comment: 7 pages, 3 figure
Mapping constrained optimization problems to quantum annealing with application to fault diagnosis
Current quantum annealing (QA) hardware suffers from practical limitations
such as finite temperature, sparse connectivity, small qubit numbers, and
control error. We propose new algorithms for mapping boolean constraint
satisfaction problems (CSPs) onto QA hardware mitigating these limitations. In
particular we develop a new embedding algorithm for mapping a CSP onto a
hardware Ising model with a fixed sparse set of interactions, and propose two
new decomposition algorithms for solving problems too large to map directly
into hardware.
The mapping technique is locally-structured, as hardware compatible Ising
models are generated for each problem constraint, and variables appearing in
different constraints are chained together using ferromagnetic couplings. In
contrast, global embedding techniques generate a hardware independent Ising
model for all the constraints, and then use a minor-embedding algorithm to
generate a hardware compatible Ising model. We give an example of a class of
CSPs for which the scaling performance of D-Wave's QA hardware using the local
mapping technique is significantly better than global embedding.
We validate the approach by applying D-Wave's hardware to circuit-based
fault-diagnosis. For circuits that embed directly, we find that the hardware is
typically able to find all solutions from a min-fault diagnosis set of size N
using 1000N samples, using an annealing rate that is 25 times faster than a
leading SAT-based sampling method. Further, we apply decomposition algorithms
to find min-cardinality faults for circuits that are up to 5 times larger than
can be solved directly on current hardware.Comment: 22 pages, 4 figure